fbpx

Date

Sep 14 2021
Expired!

Time

EDT
8:00 am - 6:00 pm

Voltage Drop and Variation-Aware Path and Clock Timing Analysis

Learn how Ansys Path FX can help you uncover silicon failures that would be missed by traditional STA flows, by accounting for both temporal and spatial variability on timing-critical paths. By capturing true post-silicon behavior, you can drastically improve the functional yield of your chips with confidence.

The event is finished.

Leave a Reply

Your email address will not be published. Required fields are marked *

Fill out this field
Fill out this field
Please enter a valid email address.
You need to agree with the terms to proceed

Menu