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Semiconductors | SoC Software

Semiconductor manufacturing and design innovations are driving the revolution in smart products via smaller device architectures and more energy-efficient devices.

In the new 3D-IC, stacked-die, and FinFET architectures, shrinking geometries mean design challenges in power and reliability, which impact design closure.

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Achieve the accuracy and performance you need to determine the power noise integrity and reliability of complex ICs with Ansys SoC software for modeling and simulation (including thermal effects, electrostatic discharge phenomena, and electromigration.)

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Electro-Thermal Design of Semiconductors | EPS Architecture

Debugging Static IR Drop | Digital Implementation

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Semiconductors Applications | SoC

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3-D IC
  • Semiconductor 3-D IC advantages include lower power, smaller form factor, and higher performance, but stacking multiple ICs or integrating them on the same package presents verification challenges.
  • Simulate multiple IC modules integrated in 3-D or 2.5-D with the Ansys RedHawk-3-D IC platform, which allows you to extract and model the package during power and signal integrity simulation.
Power Efficiency
  • Battery-powered electronics platforms, such as mobile computer platforms with several ICs on the same board, must consume power efficiently.
  • Ansys PowerArtist provides an extensive RTL design-for-power platform that debuts, analyzes, and reduces power for digital ICs. Engineers can achieve predictable power accuracy that is within 10-15% of gate-level tools for power analysis.
Power Integrity
  • Achieving operational reliability requires that proper voltage be supplied to all the devices on a System on Chip (SoC). Because of power grid design weaknesses and operation condition variations, supply voltage noise is inherent to ICs.
  • Ansys RedHawk SoC software allows engineers to accurately analyze supply voltage variations with various load conditions and to reduce overall noise.
IP Fidelity Analysis
  • For System on Chip design, semiconductor Ips are crucial parts. Engineers must analyze the Ips for their operational reliability both alone and within the System on Chip.
  • To analyze the Ips for reliability and to create an accurate model for System on Chip level verification, engineers need a robust platform.
  • Ansys Totem provides a platform for transistor-level power noise and reliability analysis for analog/mixed signal designs.
SoC Reliability
  • For SoC Software designs, semiconductor Ips are crucial parts. Engineers must analyze the Ips for their operational reliability both alone and within the System on Chip.
  • To analyze the Ips for reliability and to create an accurate model for System on Chip level verification, engineers need a robust platform like SoC software, Clock FX.
Substrate Noise
  • System on Chip semiconductor ICs are made of analog circuits, a high-speed digital core, I/O interfaces, and sensitive radio frequency modules.
  • Engineers can model noise injection from digital cores and noise propagation through silicon substrate with Ansys Canyon Substrate Extension platform.
CPS Co-Design
  • For a Chip Package System (CPS), signal and power integrity simulation for ICs should be done with the correct IC noise model and the package and board channel model.
Simulate IR Drops
  • Simulate electrical potential difference between the two ends of a conducting phase during a current flow for full chip or IP signoff with Advanced Power Analytics (APA) to provide root-cause analysis for voltage drop.
Elastic Cloud Computing
  • Engineers leverage big data analytics to simplify their verification flow on cutting-edge chips, employing simulation tools like RedHawk-SC to produce field-programmable gate arrays.