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Semiconductors

Semiconductor manufacturing and design innovations are driving the revolution in smart products via smaller device architectures and more energy-efficient devices.

In the new 3D-IC, stacked-die, and FinFET architectures, shrinking geometries mean design challenges in power and reliability, which impact design closure.

Achieve the accuracy and performance you need to determine the power noise integrity and reliability of complex ICs with Ansys software for modeling and simulation (including thermal effects, electrostatic discharge phenomena, and electromigration.)

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Semiconductors Applications

3-D IC

Semiconductor 3-D IC advantages include lower power, smaller form factor, and higher performance, but stacking multiple ICs or integrating them on the same package presents verification challenges. Simulate multiple IC modules integrated in 3-D or 2.5-D with the Ansys RedHawk-3-D IC platform, which allows you to extract and model the package during power and signal integrity simulation.

Power Efficiency

Battery-powered electronics platforms, such as mobile computer platforms with several ICs on the same board, must consume power efficiently. Ansys PowerArtist provides an extensive RTL design-for-power platform that debuts, analyzes, and reduces power for digital ICs. Engineers can achieve predictable power accuracy that is within 10-15% of gate-level tools for power analysis.

Power Integrity

Achieving operational reliability requires that proper voltage be supplied to all the devices on a System on Chip. Because of power grid design weaknesses and operation condition variations, supply voltage noise is inherent to ICs. Ansys RedHawk allows engineers to accurately analyze supply voltage variations with various load conditions and to reduce overall noise.

IP Reliability Analysis

For System on Chip design, semiconductor Ips are crucial parts. Engineers must analyze the Ips for their operational reliability both alone and within the System on Chip. To analyze the Ips for reliability and to create an accurate model for System on Chip level verification, engineers need a robust platform. Ansys Totem provides a platform for transistor-level power noise and reliability analysis for analog/mixed signal designs.

System on Chip Reliability

For System on Chip design, semiconductor Ips are crucial parts. Engineers must analyze the Ips for their operational reliability both alone and within the System on Chip. To analyze the Ips for reliability and to create an accurate model for System on Chip level verification, engineers need a robust platform. Ansys Totem provides a platform for transistor-level power noise and reliability analysis for analog/mixed signal designs.

Substrate Noise

System on Chip semiconductor ICs are made of analog circuits, a high-speed digital core, I/O interfaces, and sensitive radio frequency modules. Engineers can model noise injection from digital cores and noise propagation through silicon substrate with Ansys Canyon Substrate Extension platform.

Chip Package System Co-Design

Signal and power integrity simulation for ICs should be done with the correct IC noise model and the package and board channel model.

Semiconductors Products

RedHawk

As the de facto standard power integrity and reliability solution, Ansys RedHawk accurately predicts chip power and noise using voltage drop simulation analysis for the entire power delivery network (PDN), from chip to package to board.

Totem

Ansys Totem is a transistor-level power noise and reliability simulation platform for analog, mixed-signal and custom digital designs.

PowerArtist

Ansys PowerArtist provides early RTL power estimation and analysis-driven power reduction for RTL-to-GDS design for power methodology.

PathFinder

Ansys PathFinder simulates electrostatic discharge (ESD) in full-chip SoC and IP designs for planning, verification and sign-off.

RedHawk-SC

RedHawk-SC is the next-generation System on Chip power noise signoff platform to enable sub-16nm design success. RedHawk-SC is built on Ansys SeaScape, the world’s first custom-designed, big data architecture for electronic system design and simulation.

Path FX

Path FX complements existing sign-off and physical design flows. It has the performance to evaluate all the timing paths and clock trees in a System on Chip for delay and variance for even the largest designs.

Variance FX

Variance FX provides the most complete variation models for standard cells and custom macros. It creates both delay and constraint derates and .lib timing models for entire libraries.

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