Ansys Exalto | EM-aware Parasitic Model Extraction for SoC

Ansys Exalto is a robust post-LVS RLCk extraction software solution that enables IC design engineers to accurately predict electromagnetic coupling effects during the signoff phase.





Electrothermal Design of Power Converters for Electric Propulsion









The Gold Standard of Post-LVS RLCK Extraction Software




  • The unmatched capacity of the ANSYS modeling engine at the center of Exalto empowers engineers to analyze particularly complex layouts with ease. Complex coupling scenarios between sensitive RF circuitry with substantial digital busses/control signals are effortlessly captured using the “point-and-click” interface.
  • A distinctive netlist reduction method makes the output netlist exceptionally compact, equating to a 90% reduction in elements and nodes compared to the native netlist, which further expands the size threshold that can be fixed using Exalto.
  • Conventional RC extractors with additional high frequency (Lk) options run into a capacity bottleneck as the output netlist is too large to simulate. Netlist reduction in Exalto alleviates this issue and increases its capacity and processing capabilities by an order of magnitude.
  • Exalto interfaces effortlessly integrate with third-party LVS tools such as Cadence PVS, Mentor Graphics Calibre LVS as well as Synopsys ICV.
  • In addition, Exalto output can be automatically linked with the outputs of third-party LPE tools such as Cadence Quantus QRC, Mentor Graphics Calibre PEX and Synopsys StarRC. Exalto also supports “extracted views” as well as “extracted netlists.”

With Ansys Exalto, users you can produce:

  • Passive, causal DC accurate S-parameter models appropriate for AC, harmonic balance and SP analyses.
  • Passive, causal and highly compact RLCk netlist models appropriate for transient, shooting, as well as noise analyses
  • SPICE/SPECTRE setup and formatting RLCk netlists that can always be simulated.


  • Ansys Exalto can extract full analytical capacitive coupling between overlaying inductors with underlying devices.
  • It leverages existing foundry-characterized intra-device models for capacitors and transistors and then lumps total coupling capacitance to device terminals only.
  • Exalto has the capacity and speed to extract full capacitive coupling even for thousands of devices.
  • Run multiple “what-if” scenarios with different sets of critical nets, without ever touching your test bench schematic.
  • Exalto can extract full analytical capacitive coupling between overlaying inductors with underlying devices.