Sep 14 2021


8:00 am - 6:00 pm

Voltage Drop and Variation-Aware Path and Clock Timing Analysis

Learn how Ansys Path FX can help you uncover silicon failures that would be missed by traditional STA flows, by accounting for both temporal and spatial variability on timing-critical paths. By capturing true post-silicon behavior, you can drastically improve the functional yield of your chips with confidence.

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