Contact UsAnsys EMAG 303: Ansys SIwave – Signal Integrity Analysis
Course Overview:
This course covers the essential Signal Integrity tools in Ansys SIwave — including impedance scanning, crosstalk analysis, high-speed channel evaluation, and DDR memory validation. Each module is paired with hands-on workshops that follow real design patterns, helping engineers apply concepts directly to their own PCB layouts. The goal is to catch and fix signal integrity issues early, before hardware is built.
Who should take this course:
- PCB Designers
- Hardware Design Engineers
- PCB Layout Engineers
- Electronics Simulation Engineers
- High-Speed Digital Design Engineers
- System Architects
Core proficiencies:
- Understand the fundamental principles of signal integrity, including characteristic impedance, transmission line behavior, and electromagnetic coupling in PCB design.
- Configure and run signal integrity analyses in Ansys SIwave across all six tools covered: Zo Scan, Signal Net Analyzer, TDR Wizard, Crosstalk Scan, SI Wizard, and DDR Wizard.
- Assign and manage IBIS and AMI models for drivers, receivers, and memory devices in high-speed interface simulations.
- Interpret impedance plots, S-parameters, TDR waveforms, and crosstalk results; identify root causes and correlate findings with PCB layout decisions.
- Generate and evaluate eye diagrams; analyze jitter, noise, and BER; and verify compliance with industry standards.
- Analyze DDR memory interfaces including waveform, timing, skew, and JEDEC Virtual Compliance verification.
- Optimize PCB routing, stackup, and termination to achieve controlled impedance, reduce coupling, and eliminate signal integrity violations.
- Generate engineering reports documenting simulation results and actionable design recommendations.
Contact for EMAG 303 Training
Course Agenda | EMAG 303
Module 1: Zo Scan
- Why Zo Scan and characteristic impedance fundamentals
- Net selection, scan configuration, and solver setup
- Results: Zo plots, differential impedance, and coupled structures
- Impedance discontinuities, violations, and manufacturing effects
- Design optimization and report generation
- Tools: Stackup Editor, Layer Manager, Material Library, Design Constraints
Module 2: Signal Net Analyzer
- High-speed channel fundamentals and channel configuration
- Simulation setup and solver options
- S-parameter analysis: S11, S21, SDD21, insertion loss, and return loss
- Time-domain (TDR/TDT) and frequency-domain analysis
- Eye diagram generation and statistical analysis
- Jitter, noise, and BER analysis; compliance verification
- Tools: Channel Builder, IBIS/AMI Model Assignment, Equalization (CTLE/FFE/DFE), Compliance Testing
Module 3: TDR Wizard
- TDR fundamentals and probe placement
- Solver setup and excitation configuration
- TDR impedance profiles and reflection coefficient analysis
- Discontinuity patterns and root cause identification: vias, connectors, stubs, bends, layer transitions
- Before-and-after design comparison and report generation
- Tools: TDR Probe Manager, Differential TDR Analysis, Stackup Editor, Impedance Calculator
Module 4: Crosstalk Scan
- Electromagnetic coupling fundamentals: NEXT and FEXT
- Aggressor and victim net identification, solver setup
- Coupling results: NEXT, FEXT, violation detection, and root cause
- PCB layout optimization and before-and-after comparison
- Tools: Coupled Net Identification, Differential Pair Analysis, Stackup Editor, Design Constraints
Module 5: SI Wizard
- End-to-end SI workflow and IBIS model assignment
- Simulation setup for single-ended and differential signals
- Waveform analysis, eye diagrams, reflections, ringing, and overshoot
- Timing and delay analysis, SI violation identification
- Routing, termination, and stackup optimization
- Tools: IBIS Model Manager, Signal Classification, Differential Pair Configuration, Advanced Solver Settings
Module 6: DDR Wizard
- DDR architecture, topology, and signal classification
- IBIS model assignment for controllers and memory devices
- Read and write simulation configuration
- Waveform, eye diagram, timing, and skew analysis
- Setup/hold margins and Virtual Compliance (JEDEC verification)
- Routing, topology, and termination optimization
- Tools: DDR Wizard Workflow, IBIS/AMI Model Assignment, Virtual Compliance Report